The present invention relates to a prefetch controller and more particularly to a prefetch controller which detects a regularity of addresses of data to be accessed sequentially and then prefetches data.
A conventional cache memory controller transfers data from a storage unit to cache memory when required data is not found in the cache memory (hereafter, this condition is called a cache miss). Further, as a software-controlled method, cache data prefetch instructions specify data to be transferred from a storage unit to cache memory in advance.
However, because the cache memory controller starts accessing the storage unit upon detection of a cache miss, it takes some time for the central processing unit to receive data and therefore cannot continue execution of an instruction requiring the data. Another problem is that a cache miss, if generated on a recent central processing unit having a pipeline installed for higher throughput, sometimes stops the pipeline, degrading the performance of the central processing unit.
In the software-controlled method, cache data prefetch instructions explicitly specifying prefetch operations in a program increase the program size, degrading performance. Another problem with this method is that it is usually impossible to predict correctly where access to the storage unit will be made within the program and, therefore, it is difficult to generate prefetch instructions at correct locations within the program at compilation time.